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Science Innovation Review: Developers of Supercomputers in Russia
Issue: Volume 7, Issue 5, October 2019
Pages: 107-112
Received: 18 August 2019
Accepted: 23 September 2019
Published: 14 October 2019
DOI:
10.11648/j.jeee.20190705.12
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Abstract: Author describes developers of supercomputers in Russia. The situation of a significant predominance of the field of science and education in the use of supercomputers in Russia was created artificially. Author believes that it will gradually improve in the natural process of state development. Due to the fact that the limit of miniaturization of the elemental base on the basis of silicon complementary metal-oxide-semiconductor (CMOS) technologies is approaching, i.e. the end of Moore’s law is approaching (in the region of 2024, currently 22nm, the expected limit is 5 nm in 2020), in foreign countries, parallel to exaflops projects, work is underway on the promising element-design base of the Post-Moore’s era. New application areas may require the creation of cluster supercomputers that differ from most modern ones oriented to high-performance computing, as well as supercomputers that differ from cluster ones, i.e. on a special element base and other special solutions, both in hardware and in software. This, in fact, is happening now in the United States and China. Author shows examples of the development in the world and in Russia of new applied areas for the use of supercomputer resources and these resources themselves. A complete solution to the protection problem is the development of supercomputers with hardware-based security levels for programs and data.
Abstract: Author describes developers of supercomputers in Russia. The situation of a significant predominance of the field of science and education in the use of supercomputers in Russia was created artificially. Author believes that it will gradually improve in the natural process of state development. Due to the fact that the limit of miniaturization of t...
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Analysis of World Experience in Creating Parallel Computing Systems Designed to Effectively Solve DIS-tasks
Issue: Volume 7, Issue 5, October 2019
Pages: 101-106
Received: 22 August 2019
Accepted: 23 September 2019
Published: 09 October 2019
DOI:
10.11648/j.jeee.20190705.11
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Abstract: Author describes world experience in creating parallel computing systems by example Cray XE6 and network chip Gemini, designed to effectively solve Data intensive tasks (DIS-tasks). Most often, in modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory. It is possible to provide support for a programming model with shared (shared) memory in various ways using hardware, as well as using virtualization software. Different options for implementing a shared memory programming model may vary in functionality and timing of memory accesses. The problem of the “memory wall” is that if arithmetic-logical operations take several processor cycles, then operations directly with the memory take several hundred cycles. If the memory is formed from the memories of computing nodes connected by a communication network, then the execution time of such a call includes the time of operation with the network to transfer addresses and data. This already increases the memory access time to several thousand cycles. The problem is that such delays in accessing data cause idle functional units of the processor - they cannot perform arithmetic and logical operations on data, because they simply do not exist due to the large delays in performing operations with memory.
Abstract: Author describes world experience in creating parallel computing systems by example Cray XE6 and network chip Gemini, designed to effectively solve Data intensive tasks (DIS-tasks). Most often, in modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive compl...
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New-age Supercomputers: Hi-Speed Networks and Information Security
Issue: Volume 7, Issue 3, June 2019
Pages: 82-86
Received: 18 August 2019
Accepted: 21 September 2019
Published: 09 October 2019
DOI:
10.11648/j.jeee.20190703.12
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Abstract: The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabilities. Machines of this segment are also called High End Computers (HEC), and in our terminology - strategic supercomputers (SCs). Moving to the engineering level, author says that for tasks with good spatio-temporal work with memory, cache memory and schemes for automatically pre-loading data into the cache memory can be effectively used. This can significantly reduce the average memory access time of several hundred processor cycles to fractions of a processor cycle. Such tasks are usually called computational or cache-friendly (cach-friendly) - CF tasks. On tasks with poor spatio-temporal work with memory, the cache memory is useless, so each memory access is hundreds of processor cycles, the processor is idle because of this, and therefore the real performance is in units or even a fraction of a percent of the peak. Such tasks are historically called tasks with intensive irregular work with memory – Data intensive tasks (DIS-tasks). The given examples of spatially-temporal work with task memory and real characteristics of equipment operation in such different modes are given in order to illustrate that in practice different types of supercomputers are needed, for example, for CF- and DIS-tasks.
Abstract: The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabi...
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Age of Great Chinese Dragon: Supercomputer Centers and High Performance Computing
Issue: Volume 7, Issue 4, August 2019
Pages: 87-94
Received: 18 August 2019
Accepted: 21 September 2019
Published: 09 October 2019
DOI:
10.11648/j.jeee.20190704.11
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Abstract: Author describes Chinese supercomputer centers and networks. There are currently five National Supercomputing Centers in China, which are established in Tianjin, Shenzhen, Shanghai, Jinan, and Chang-Sha. These cities were selected as pilot ones for conducting an experiment on the development of the cloud computing services market. The directions of evolutionary and innovative development of exaflops supercomputers are highlighted in Pacific region. The evolutionary approach is the simplest and allows you to quickly get the result, but the created supercomputer of this type will be effective only when solving a narrow class of problems and have low energy efficiency. An innovative approach involves basic research and the development of innovative technologies, which is much more complicated and requires more time. Innovative technologies for the development of exaflops supercomputers, due to the stringent requirements of energy efficiency and productivity efficiency, have much in common with technologies for creating highly efficient on-board and embedded systems. These technologies are called exascale, they should provide the ability to create single-board on-board supercomputers of the teraflops level and single-rack supercomputers of the petaflops level of performance. The main problems of creating exaflops (exascale) systems: increasing the overall performance of the system by three orders of magnitude while weakening the influence of Moore's law on the performance of an individual processor core; minimization of energy losses and performance losses associated with data access, information transfer at all levels of the supercomputer hierarchy and data storage.
Abstract: Author describes Chinese supercomputer centers and networks. There are currently five National Supercomputing Centers in China, which are established in Tianjin, Shenzhen, Shanghai, Jinan, and Chang-Sha. These cities were selected as pilot ones for conducting an experiment on the development of the cloud computing services market. The directions of...
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China Net: Military and Special Supercomputer Centers
Issue: Volume 7, Issue 4, August 2019
Pages: 95-100
Received: 18 August 2019
Accepted: 23 September 2019
Published: 09 October 2019
DOI:
10.11648/j.jeee.20190704.12
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Abstract: Author describes military and special supercomputer centers and networks by example CT-2. Work on highly productive and promising SC with a globally addressable memory and multi-thread architecture is carried out within the framework of the CT-2 project. The eponymous supercomputer belongs to the class of strategic supercomputers. The code name used is CT-2 (full name Qin Tao -2) - this is the idiom in the Chinese name “The main project in the interests of special studies of military intelligence of the Ministry of Defense of China”. Due to using of massive multi-thread streaming architecture increased tolerance to delays in performing operations with memory and the network, effectively support working with program models in the form of static graphs of data flows. Because of this, it will successfully cope with the processing in real time of multiple data streams and work effectively through a single address space with a huge memory capacity of several tens of petabytes, even in the mode of intensive irregular work with it, it will have exceptional fault tolerance and availability. The amount of available memory for the user program is 32PB, the physical memory is 64PB, which is done for hot standby. According to information received in 2011, the initially massive multi-thread microprocessor CT-2 with asynchronous threads for information systems has also become hybrid, it has enhanced numerical processing power - SIMD operations on short vectors have been introduced, as well as elements of modern graphic processors in the form of synchronous threads.
Abstract: Author describes military and special supercomputer centers and networks by example CT-2. Work on highly productive and promising SC with a globally addressable memory and multi-thread architecture is carried out within the framework of the CT-2 project. The eponymous supercomputer belongs to the class of strategic supercomputers. The code name use...
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