Analysis of World Experience in Creating Parallel Computing Systems Designed to Effectively Solve DIS-tasks
Journal of Electrical and Electronic Engineering
Volume 7, Issue 5, October 2019, Pages: 101-106
Received: Aug. 22, 2019;
Accepted: Sep. 23, 2019;
Published: Oct. 9, 2019
Views 380 Downloads 106
Andrey Molyakov, Institute of Information Technologies and Cybersecurity, Russian State University for the Humanities, Moscow, Russia
Author describes world experience in creating parallel computing systems by example Cray XE6 and network chip Gemini, designed to effectively solve Data intensive tasks (DIS-tasks). Most often, in modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory. It is possible to provide support for a programming model with shared (shared) memory in various ways using hardware, as well as using virtualization software. Different options for implementing a shared memory programming model may vary in functionality and timing of memory accesses. The problem of the “memory wall” is that if arithmetic-logical operations take several processor cycles, then operations directly with the memory take several hundred cycles. If the memory is formed from the memories of computing nodes connected by a communication network, then the execution time of such a call includes the time of operation with the network to transfer addresses and data. This already increases the memory access time to several thousand cycles. The problem is that such delays in accessing data cause idle functional units of the processor - they cannot perform arithmetic and logical operations on data, because they simply do not exist due to the large delays in performing operations with memory.
Analysis of World Experience in Creating Parallel Computing Systems Designed to Effectively Solve DIS-tasks, Journal of Electrical and Electronic Engineering. Special Issue: Science Innovation.
Vol. 7, No. 5,
2019, pp. 101-106.
Copyright © 2019 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/
) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Cray’s Baker pops out of the oven as company «re-learns» how to make great systems, by John West, 06. 28. 2010, http://insidehpc.com/category/business-of-hpc.
Cray launches Gemini super interconnect, Timothy Prickett Morgan, Posted in HPC, 25 May 2010, www.theregister.co.uk/2010/05/25/cray_xe6_baker_gemini/page2.html.
Cray Unveils "Baker" Supercomputer, by Michael Feldman, HPCwire, May 25, 2010, www.hpcwire.com/features/94828804.html.
Shahbazi Karim, Eshghi Mohammad, Mirzaee Reza Faghih. Design and Implementation of ASIP-based cryptography processor for AES, IDEA, and MD5. Engineering Science and Technology, an International Journal, 20, 2017, 1308-1317.
NSF Awards PSC $2.8M toward the Purchase of World’s Largest Coherent Shared-Memory System, July 29, 2010.
SGI ASIC is first step to exascale system, Rick Merritt, 9/9/2010, www.eetimes.com/electronics-news/4207500/SGI-ASIC-is-first-step-to-exascale-system.
SGI Colors New Shared Memory Machines Ultraviolet, by Michael Feldman, HPCwire, November 16, 2009, www.hpcwire.com/features/SGI-Colors-New-Shared-Memory-Machines-Ultraviolet-70198797.html.
Molyakov, А. S. New Multilevel Architecture of Secured Supercomputers/A. S. Molyakov//Current Trends in Computer Sciences & Applications 1 (3) – 2019. – PP. 57-59. – ISSN: 2643-6744 – https://lupinepublishers.com/computer-science-journal/special-issue/CTCSA.MS.ID.000112.pdf. – DOI: 10.32474/CTCSA.2019.01.000112.
Molyakov, A. S. Technological Methods Analysis in the Field of Exaflops Supercomputers Development Approaching/A. S. Molyakov, L. K. Eisymont//Global Journal of Computer Science and Technology: Information & Technology. – 2017. – № 1 (17). – РР. 37-44.
Molyakov, A. S. A Prototype Computer with Non-von Neumann Architecture Based on Strategic Domestic J7 Microprocessor/A. S. Molyakov//Automatic Control and Computer Sciences. – 2016. – № 50 (8). – РР. 682-686.
Molyakov, A. S. Token Scanning as a New Scientific Approach in the Creation of Protected Systems: A New Generation OS MICROTEK/A. S. Molyakov//Automatic Control and Computer Sciences. – 2016. – № 50 (8). – РР. 687-692.
Molyakov, A. S. Model of hidden IT security threats in the cloud computing environment/A. S. Molyakov, V. S. Zaborovsky, A. A. Lukashin//Automatic Control and Computer Sciences. – 2015. – № 49 (8). – РР. 741-744.
Alam S. R., Barrett R. F., McCurdy C. B., Roth P. C., Vetter J. S. Characterizing Applications on the Cray MTA-2 Multithreading Architecture. ORNL, Cray User Conference, 2006, 13 pp.
Taylor M. B. Bitcoin and the Age of Bespoke Silicon. Proc Int’l Conf. Compilers, Architectures and Systems for Embedded Systems. 2013, 9 pp.
Trader T. STARnet Alliance Seeks Revolution in Chip Design. HPCWire, January 23, 2013.