Please enter verification code
Confirm
Cache Optimization by Fully-Replacement Policy
American Journal of Embedded Systems and Applications
Volume 4, Issue 1, November 2016, Pages: 7-14
Received: Oct. 20, 2016; Accepted: Nov. 9, 2016; Published: Dec. 5, 2016
Views 4212      Downloads 102
Authors
Chuntao Du, Department of Computer Science and Technology, North China University of Technology, Beijing, China
Xinsong Du, Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida, USA
Article Tools
Follow on us
Abstract
Cache is an important component in computer architecture. It has great effects on the performance of systems. Nowadays, Least Recently Used (LRU) Algorithm is one of the most commonly used one because it is easy to implement and with a relatively good performance. However, in some particular cases, LRU is not a good choice. To provide references for the computer architecture designer, the study proposed a new algorithm named Fully Replacement Policy (FRP) and then analyzed various factors of effects on cache performance, carried out the simulation experiment of cache performance based on SimpleScalar toolset and SPEC2000 benchmark suite. The study compared the effects of Fully Replacement Policy with Least Recently Used (LRU) Algorithm when set size, block size, associativity and replacement methods are changed separately., By experimentally analyzing the results, it was found that FRP outperforms LRU in some particular situations.
Keywords
Cache memory, Replacement, Optimization, SimpleScaler, SPEC2000
To cite this article
Chuntao Du, Xinsong Du, Cache Optimization by Fully-Replacement Policy, American Journal of Embedded Systems and Applications. Vol. 4, No. 1, 2016, pp. 7-14. doi: 10.11648/j.ajesa.20160401.12
Copyright
Copyright © 2016 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
References
[1]
Appuswamy R, Moolenbroek D C V, Tanenbaum A S. Cache, cache everywhere, flushing all hits down the sink: On exclusivity in multilevel, hybrid caches[J]. 2013: 1-14.
[2]
Jouppi, Norman P.“Improving Direct-Mapped Cache Performance by the Addition of a SmallFully-Associative Cache and Prefetch Buffers.” In Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on, 364–73. IEEE, 1990. Geoffrey E. Hinton, and Ruslan R. Salakhutdinov. Reducing the dimensionality of data with neural networks. Science 313.5786 (2006): 504~507.
[3]
Waseem Ahmad, Enrico Ng. "A Quantitative/Qualitative Study for Optimal Parameter Selection of a Superscalar Processor using SimpleScalar". Computer Sciences Technical Report, 2004.
[4]
A. J Klein Osowski, J. Flynn, N. Meares, and D. J. Lilja. Adapting the SPEC2000 benchmark suite for simulation-based computer architecture research. In Workshop on Workload Characterization, 2000.
[5]
Yu Zhi-Bin, Jin Hai, Zou Nan-Hai. "Computer architecture software-based simulation". Journal of Software, 2008, 19(4), pp. 1051-1068.
[6]
Doug Burger, Todd M. Austin, The SimpleScalar tool set, version 2.0, ACM SIGARCH Computer Architecture News, v.25 n.3, p.13-25, June 1997 [doi>10.1145/268806.268810].
[7]
Austin B T M, Burger D, Franklin M, et al. Skadron, "The SimpleScalar Architectural Research Tool Set," http://www.cs.wisc.edu/~mscalar/ simplescalar. html, retrieved April 24[J]. 2010.
[8]
Austin T, Larson E, Dan E. Simplescalar: “An Infrastructure for Computer System Modeling” [J]. Computer, 2002, 35(2): 59-67.
[9]
Kalaitzidis K, Dimitriou G, Stamoulis G, et al. Performance and power simulation of a functional-unit-network processor with simplescalar and wattch[C]// The, Panhellenic Conference. 2015: 71-76.
[10]
J. Cantin, and M. Hill, "Cache Performance for SPEC CPU 2000 Benchmarks" http://www.cs.wisc.edu/multifacet/miso/spec2000 cache-data/
[11]
S. Sair and M. Charney. Memory behavior of the SPEC2000 benchmark suite. Technical report, IBM, 2000.
[12]
D. Citron, "MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences", Proc. of International Symposium on Computer Architecture, pp. 52-61, 2003.
ADDRESS
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
U.S.A.
Tel: (001)347-983-5186