Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications
International Journal of Materials Science and Applications
Volume 7, Issue 5, September 2018, Pages: 167-173
Received: Jul. 31, 2018; Accepted: Aug. 27, 2018; Published: Sep. 28, 2018
Views 1135      Downloads 127
Muhammad Sana Ullah, Department of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, USA
Emadelden Fouad, Department of Natural Science, Florida Polytechnic University, Lakeland, USA
Article Tools
Follow on us
Continuous reducing the size of transistor technology has enabled extraordinary improvements in the switching speed, density, functionality and cost of microprocessors. Integrated Circuit industry is pursuing Moore’s curve down to deep-nanoscale dimensions. Advanced transistor technology now faces many challenges that together result in static power consumption due to leakage currents. In fact, leakage currents are responsible for more than 50% of the total power consumption in nanoscale designs. In deep-nanoscale arena, this percentage will increase further. However, diagnosing of the interface quality and interaction between insulators and semiconductors is significant to reduce the leakage current and achieve the high performance of switching devices in the nanoscale domain. Continuous scaling down has required drastic decreases of the SiO2 dielectric film thickness to achieve ever-higher capacitance densities. Fundamental limits of SiO2 as a dielectric material, imposed by electron tunneling, will be reached as this SiO2 film thickness approaches ~1nm. Therefore, alternate high-k interlayer dielectric material will be needed to replace SiO2 as a capacitor and gate dielectric material. Numerous alternate high-k materials are being actively investigated, ranging from Al2O3 (k ~ 9) to HfO2 (k ~ 25). High-k materials hold the promise of achieving very high capacitance densities with relatively thick films.
Dielectric Materials, High-k Materials, Hafnium Oxide, MOS Transistor, Nanoscale Domain
To cite this article
Muhammad Sana Ullah, Emadelden Fouad, Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications, International Journal of Materials Science and Applications. Vol. 7, No. 5, 2018, pp. 167-173. doi: 10.11648/j.ijmsa.20180705.11
Copyright © 2018 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License ( which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: current status and materials properties considerations,” J. Appl. Phys., vol. 89, pp. 5243–5275, 2001.
H. S. Nalwa, Handbook of Low and High Dielectric Constant Materials and Their Applications, Volume 1: Materials and Processing. Academic Press, San Diego, CA. 1999.
R. Singh and R. K. Ulrich, “High and low dielectric constant materials,” Electrochemical Society Interface, vol. 8, pp. 26–30, 1999.
M. Ritala, and M. Leskela, “Atomic layer deposition. In Handbook of Thin Film Materials,” Academic Press, San Diego, CA, vol. 1, pp. 103, 2001.
A. Rahtu, M. Ritala and M. Leskela, “Atomic layer deposition of zirconium titanium oxide from titanium isopropoxide and zirconium chloride,” Chem. Mater., vol. 13, pp. 1528–1532, 2001.
P. Singer, “Intel, IBM commit to high-k, metal gates,” Semiconductor International, 2007.
S. Ogura, P.J. Tsang, W. W. Walker, D. L. Critchlow and J. F. Shepard, “Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor,” IEEE Transactions on Electron Device, vol. 27, no. 8, pp. 1359-1367, 1980.
H. J. Choi, J. G. Lee and Y. W. Kim, “High Temperature Strength and Oxidation Behavior of Hot-Pressed Silicon Nitride-Disilicate Ceramics,” Journal of Materials Science, vol. 32, no. 7, pp. 1937-1942, 1997.
Y. S. Zheng, K. M. Knowles, J. M. Vieira, A. B. Lopes and F. J. Oliveira, “Microstructure, Toughness and Flexural Strength of Self-Reinforced Silicon Nitride Ceramics Doped with Yttrium Oxide and Ytterbium Oxide,” Journal of Microscopy, vol. 201, no. 2, pp. 238-249, 2001.
I. Khan and M Zulfequar, “Effect of Tellurium on Electrical and Structural Properties of Sintered Silicon Nitride Ceramics,” Physica B, Vol. 404, No. 16, pp. 2395- 3400, 2009.
Y. Zhang, Y. B. Cheng S. Lathabai and K. Hirao, “Erosion Response of Highly Anisotropic Silicon Nitride,” Journal of the American Ceramic Society, Vol. 88, No. 1, pp. 114-120, 2005.
A. Vuckovic, S. Boskovic and L. Zivkovic, “Synthesis of ‘in-Situ’ Reinforced Silicon Nitride Composites,” Journal of the Serbian Chemical Society, Vol. 69, No. 1, pp. 59-67, 2004.
E.H. Kisi and C.J. Howard, “Crystal structure of zirconia phases and interrelation,” Key. Eng. Mater., vol. 153, pp. 1–36, 1998.
J.P. Chang, Y.S. Lin, S. Berger, A. Kepten, R. Bloom, and S. Levy, “Ultrathin zirconium oxide films as alternative gate dielectric,” J. Vac. Sci. Technol., vol. 19, no. 6, pp. 2212 , 2001.
X. Zhao, D. Ceresoli, and D. Vanderbilt, “Structural, electronic, and dielectric properties of amorphous ZrO2 ab initio molecular dynamics,” Phys. Rev., B-71, 085107, 2005.
M.V. Fischetti, “Long range Coulomb interactions in small Si-devices. Part II. Effective electron mobility in thin-oxide structures,” J. Appl. Phys., vol. 89, no. 2, pp. 1232-1250, 2001.
B.H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, J. C. Lee, “Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric applications,” IEEE IEDM Technical Digest, Washington, DC, USA, pp. 133-136, 5-8 December 1999.
A. Kingon, J. Maria, and S. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature, vol. 406, pp.1032–1038, 2000.
A. Agarwal et al., “Leakage power analysis and reduction: Models, Estimation and Tools,” Proceedings of the IEEE, vol. 152, no. 3, pp. 353-368, May 2005.
B. J. Sheu et al., “BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors,” IEEE Journal of Solid State Circuits, New York, vol.SC-22, no.4, pp. 558-566, Aug. 1987.
K. Roy et al., “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,” Proceedings of IEEE, New York, vol.91, no.2, pp. 305-327, Feb 2003.
S. Mukhopadhyay et al. “Accurate Estimation of Total Leakage in Nanometer-Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile,” IEEE Trans. On CAD of IC and Systems, New York, vol.24, no.3, pp. 363-381, March 2005.
Manorama, P. Shrivastava, and S. Akashe, “Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology,” IEEE 7th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, 4-5 January 2013.
P. Dwivedi, K. Kumar and A. Islam, “Comparative study of subthreshold leakage in CNFET & MOSFET @ 32-nm technology node,” IEEE International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, India, 23-25 January 2016.
H. Ayano, K. Murakami, Y. Matsui, “A novel technique for reducing leakage current by application of zero-sequence voltage,” International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), Hiroshima, Japan, 18-21 May 2014.
P. Verma A. K. Sharma, V. S. Pandey A. Noor and A. Tanwar, “Estimation of leakage power and delay in CMOS circuits using parametric variation,” Perspectives in Science, Elsevier, vol. 8, pp. 760-763, September 2016.
B. V. Subramanyam and S. S. Basha, “Design of low leakage power SRAM using multithreshold technique,” IEEE 10th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, 7-8 January 2016.
H. D. Tsague and B. Twala, “First principle leakage current reduction technique for CMOS devices,” IEEE International Conference on Computing, Communication and Security (ICCCS), Pamplemousses, Mauritius, 4-5 December 2015.
B. Zaidi, I. Saouane, C. Shekhar, “Simulation of Single-Diode Equivalent Model of Polycrystalline Silicon Solar Cells,” International Journal of Materials Science and Applications, Special Issue: Energy and Materials II. vol. 7, no. 1-1, pp. 8-10, 2018.
T. M. Masiala, A. K. M. Bantu, G. E. Bakambo, J. M. Lunguya, J. L. K. Kanza, O. M. Muamba, “Influence of pH Preparation on the Photo-Response of Electrodeposited Titanium Dioxide (TiO2) Thin Films,” International Journal of Materials Science and Applications, vol. 5, no. 5, pp. 207-213, 2016.
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
Tel: (001)347-983-5186